As processes of fabricating semi-conductor chips have become progressively sophisticated, the sizes of semi-conductor chips have decreased. For example, processes are now in use where the thicknesses of wires in semi-conductor circuits are less than one micron (1 .mu.). This has allowed the number of semi-conductors on a chip to increase so that tens of thousands of transistors exist on a rectangular chip with dimensions of approximately one quarter of an inch (1/4 ) on each side.
Because of the resultant increase in complexity in the circuitry on the chip, the number of external connections to the electrical circuitry on semi-conductor chips has increased as the micron size of the wires on the chips has decreased. With micron sizes of one micron (1 .mu.) or less, hundred of pads are now often disposed on the periphery of the chips to provide connections to apparatus external to the chips.
The frequencies of the electrical circuitry on the chips have also increased as the micron size of the wires on the chips has decreased. For example, where just a few years ago, frequencies in excess of fifty megahertz (50 mHz) were considered to be unattainable for micron sizes of approximately two microns (2 .mu.) in CMOS technology, frequencies in the hundreds of millions of megahertz are now attainable with micron sizes of approximately eight tenths of a micron (0.8 .mu.) in such technology.
As the frequencies of the circuitry on a chip have increased and the number of pads on the chip for connections to apparatus external to the chip have increased, it has become increasingly difficult to provide equipment for testing the chip. This has been particularly true when it has been desired to test the chips on an automatic basis with a minimal error and in a minimal time. By "automatic", it is meant that the chip is disposed in the test equipment and all of the tests are performed without human intervention after the test equipment is activated. The tests have be performed in a minimal time since the test equipment is quite expensive and tens of thousands of chips of a particular model or design are often produced.
As will be appreciated, it is often at least as difficult to provide satisfactory test equipment as it is to design semi-conductor chips. After all, the circuitry on the test equipments have to operate at least at the highest frequency attainable by the circuitry on the semi-conductor chips in order for the semi-conductor chips to be tested under operative conditions. Furthermore, the test equipment has to be able to establish electrical continuity with the individual pads on the semi-conductor chips while maintaining electrical isolation between adjacent pads on the chips.
There are two (2) types of test equipment now in use. In one type of test equipment, the same circuitry is used to make individual tests on different parts of the semi-conductor chip. Delays have accordingly to be provided in the operation of the test circuitry so that the individual tests on the different parts of the semi-conductor chip can be performed in sequence. This type of test equipment has been primarily used in the past and is still in use to a considerable extent.
In the other type of test equipment, each part of the semi-conductor chip is tested by different circuitry. The use of this type of test equipment is increasing. This type of test equipment is disadvantageous in that it is relatively expensive. However, the tests are performed in a minimal amount of time since all of the tests are performed simultaneously.
In both types of test equipment, delays have to be provided in the operation of the test circuitry in order to perform the tests satisfactorily. The delays are provided to determine if the circuitry on the chip being tested meets performance criteria specified for such circuitry. The delays have to be provided "on the fly". In other words, the delay element has to provide a uniquely programmed delay value for each input pulse. This requires the delay element to change its delay value at the same frequency as the input pulse frequency. The delays have to be precise in order to assure that the tests of the circuitry on the semi-conductor chip are performed satisfactorily and reliably under actual operating conditions.
Delay elements have generally been operated until now on an analog basis. In other words, analog signals have been introduced to the delay element to produce delays dependent upon the magnitude of the analog signals. As will be appreciated, the delays have not been precise. This has resulted from the fact that analog signals are not precise and that responses on an analog basis in delay elements to imprecise analog signals have been even less precise. For example, a change from a value of "67" to a value of "68" on an analog basis is not precise and the change in response of a delay element from an imprecise analog value of "67" to an imprecise analog value of "68" has been even less precise.
It has been appreciated for some time that delays obtained from analog signals have been less precise than would ordinarily be desired. A considerable effort has been made to provide delay systems which overcome the disadvantages specified above. For example, an approach has been tried in which a gate is used as the basic delay element. Delay variations on the gate are obtained by adjusting the load on the gate. By this approach, it is possible to provide a family of gates each with a slightly greater gate propagation delay than the previous gates in the family. Once the gates have been designed, the delay values in the gates can be binarily weighted. Then a multiplexing scheme can select the appropriate tap locations to pick off the delayed signal. The problem with this approach is its inherent non-monotonicity. This approach requires binarily weighted gate delays and tap multiplexing to provide delay matching to better than the resolution of the delay element. This could require gate delay matching within picoseconds. Furthermore, since a calibration scheme is required, this approach requires a large size and further requires a cost overhead attributable to the time involved in calibration.